http://dspace.ediindia.ac.in:8181/xmlui//handle/123456789/9691 2026-05-15T12:49:24Z 2026-05-15T12:49:24Z Gheewala, Vicky Diwan, Jayesh Chaudhary, Kalpesh http://dspace.ediindia.ac.in:8181/xmlui//handle/123456789/9726 2019-11-21T16:34:34Z 2019-06-06T00:00:00Z

Design and Implementation of Packet Routing Algorithm with Packet Error detection Logic for NOC and Verification in System Verilog Gheewala, Vicky; Diwan, Jayesh; Chaudhary, Kalpesh Network on chip (NoC) is one of the proficient on-chip correspondence design for system on chip (SoC) where an extensive number of computational and capacity blocks are incorporated on a single chip. NoCs have handled the inconveniences of SoCs just as they are adaptable. Variable on-chip communication is basic for exploiting stupendous processing power obtainable on a multi-center chip. Routing algorithms assume a genuine job for the communication quality and execution of the on-chip interconnection systems. NoC to decouple communication from computations. Router is a spine of NoC, consequently, proficient plan of router is basic to improve the execution of the system. In the present work, we focus on router input-output convention (protocol) structure. Proposed framework incorporates virtual slice through instrument for close loop communication. Router 1×3 has single information port and three output ports. Top-level architecture designed with sub-modules like FIFO, FSM, synchronizer, and register utilize Verilog language. Router RTL designed analyzed and verified utilizing Xilinx 14.7 Artix-7- XC7A100T FPGA family. Coverage is an estimation to survey the progression of useful check development. This expects a main work to obtain a sensible image on how well the structure has been confirmed. Code coverage is a fundamental coverage variety which is gathered consequently. It uncovers to you how well your Verilog code has been practiced by your testbench. Design and verify the functionality of the “packet algorithm with packet error detection logic for NOC”. We will implement class-based layer testbench with constraint random verification and coveragedriven verification.

2019-06-06T00:00:00Z Kumbhani, Krupa Shah, Milind http://dspace.ediindia.ac.in:8181/xmlui//handle/123456789/9725 2019-11-21T16:31:15Z 2019-06-06T00:00:00Z

TCAD Calibration and Simulation of Mosfet Device Kumbhani, Krupa; Shah, Milind This paper presents the calibration of Technology Computer Aided Design (TCAD) device simulator for MOSFET device and validation of this calibrated deck. MOSFET device with 350 nm gate length is actualized using SCLs process flow and compared with experimental data using specific calibration methodology. We have obtained a physically significant match with the measurement data by manipulating physical models as a fitting parameter. Thus, the same set of model parameters is anticipated to be convenient, even once ever – changing to the more device generations. We have confirmed it by comparing measurement and simulation data for 2D RESURF LDMOS device with same calibrated deck.

2019-06-06T00:00:00Z Isarani, Bhumika M Chaudhari, Vishnu Neelakantan, Usha Joshi, H C http://dspace.ediindia.ac.in:8181/xmlui//handle/123456789/9724 2019-11-21T16:29:11Z 2019-06-06T00:00:00Z

Performance Analysis of Avalanche Photo-Diode Detector Based Low Noise Optical Receiver Isarani, Bhumika M; Chaudhari, Vishnu; Neelakantan, Usha; Joshi, H C An avalanche photodiode (APD) detector is a sensitive photon detector when operated near breakdown voltage to achieve the highest internal gain. Due to low level of output from the APD, it is required to add trans-impedance amplifier (TIA) and cascaded stage of post-amplifier (PA) for amplification in addition to bias supply circuit for the design of optical receiver. The noise contribution from each component of the optical receiver is required to perform for low-level light detection application. At higher operating gain, the APD also contributes to the total noise level. In this paper, we have described the detail about circuit, simulation of the equivalent circuit of detector, detail noise calculations with bandwidth of more than 1 MHz, and frequency response of the receiver. The in-house proto-type circuit is successfully tested with APD for the detection of photons given from the fibre-optic with the laser diode as an optical source in laboratory. We believe that the work described here will find application in medical instrumentation, automobile industry, and signal communication area.

2019-06-06T00:00:00Z Mehta, Anusha Parmar, Viral D http://dspace.ediindia.ac.in:8181/xmlui//handle/123456789/9723 2019-11-21T16:24:09Z 2019-06-06T00:00:00Z

A Survey on Capsule Networks Mehta, Anusha; Parmar, Viral D In today’s digital era, machine intelligence is equally as important as human intelligence. The emergence of deep learning techniques makes machine intelligence tasks easier and better. Deep convolutional neural networks are prominent in tasks of object detection, image classification, object segmentation, and so on. Recently, Hinton and his team introduced a new architecture called capsule networks. Capsule networks replace the neurons with capsules and overcome spatial and rotational invariance limitations of convolutional neural networks. This paper defines the introduction and working of capsule networks with related work in the field of capsule network.

2019-06-06T00:00:00Z